Sumanta Pyne. Rescheduling of Power Gating Instructions for Reduction of In-rush Current. In 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018. pages 25-30, IEEE Computer Society, 2018. [doi]
@inproceedings{Pyne18,
title = {Rescheduling of Power Gating Instructions for Reduction of In-rush Current},
author = {Sumanta Pyne},
year = {2018},
doi = {10.1109/VLSID.2018.32},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2018.32},
researchr = {https://researchr.org/publication/Pyne18},
cites = {0},
citedby = {0},
pages = {25-30},
booktitle = {31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018},
publisher = {IEEE Computer Society},
isbn = {978-1-5386-3692-3},
}