Single event double node upset tolerance in MOS/spintronic sequential and combinational logic circuits

Ramin Rajaei. Single event double node upset tolerance in MOS/spintronic sequential and combinational logic circuits. Microelectronics Reliability, 69:109-114, 2017. [doi]

Authors

Ramin Rajaei

This author has not been identified. Look up 'Ramin Rajaei' in Google