A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs

Srilata Raman, C. L. Liu, Larry G. Jones. A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs. In 1996 European Design and Test Conference, ED&TC 1996, Paris, France, March 11-14, 1996. pages 170-175, IEEE Computer Society, 1996. [doi]

@inproceedings{RamanLJ96,
  title = {A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs},
  author = {Srilata Raman and C. L. Liu and Larry G. Jones},
  year = {1996},
  doi = {10.1109/EDTC.1996.494144},
  url = {http://doi.ieeecomputersociety.org/10.1109/EDTC.1996.494144},
  researchr = {https://researchr.org/publication/RamanLJ96},
  cites = {0},
  citedby = {0},
  pages = {170-175},
  booktitle = {1996 European Design and Test Conference, ED&TC 1996, Paris, France, March 11-14, 1996},
  publisher = {IEEE Computer Society},
  isbn = {0-8186-7423-7},
}