Vikas Rana. Area Efficient NMOS Based Positive and Negative Voltage Multiplier. In 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018. pages 10-15, IEEE Computer Society, 2018. [doi]
@inproceedings{Rana18-0, title = {Area Efficient NMOS Based Positive and Negative Voltage Multiplier}, author = {Vikas Rana}, year = {2018}, doi = {10.1109/ISVLSI.2018.00013}, url = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2018.00013}, researchr = {https://researchr.org/publication/Rana18-0}, cites = {0}, citedby = {0}, pages = {10-15}, booktitle = {2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018}, publisher = {IEEE Computer Society}, isbn = {978-1-5386-7099-6}, }