A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl

Marcin Rogawski, Kris Gaj, Ekawat Homsirikamol. A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl. Microprocessors and Microsystems, 37(6-7):572-582, 2013. [doi]

@article{RogawskiGH13,
  title = {A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl},
  author = {Marcin Rogawski and Kris Gaj and Ekawat Homsirikamol},
  year = {2013},
  doi = {10.1016/j.micpro.2013.05.005},
  url = {http://dx.doi.org/10.1016/j.micpro.2013.05.005},
  researchr = {https://researchr.org/publication/RogawskiGH13},
  cites = {0},
  citedby = {0},
  journal = {Microprocessors and Microsystems},
  volume = {37},
  number = {6-7},
  pages = {572-582},
}