High-speed Instruction-set Coprocessor for Lattice-based Key Encapsulation Mechanism: Saber in Hardware

Sujoy Sinha Roy, Andrea Basso. High-speed Instruction-set Coprocessor for Lattice-based Key Encapsulation Mechanism: Saber in Hardware. IACR Cryptology ePrint Archive, 2020:434, 2020. [doi]

@article{RoyB20-2,
  title = {High-speed Instruction-set Coprocessor for Lattice-based Key Encapsulation Mechanism: Saber in Hardware},
  author = {Sujoy Sinha Roy and Andrea Basso},
  year = {2020},
  url = {https://eprint.iacr.org/2020/434},
  researchr = {https://researchr.org/publication/RoyB20-2},
  cites = {0},
  citedby = {0},
  journal = {IACR Cryptology ePrint Archive},
  volume = {2020},
  pages = {434},
}