A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power - researchr publication authors

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Alessio Santiccioli, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino. A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. In IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019. pages 1-4, IEEE, 2019. [doi]

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