A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2 - researchr publication authors

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Jin-Cheol Seo, Sang-Soon Im, Kwan Yoon, Seung-Wook Oh, Taek-Joon An, Gi-Yeol Bae, Jin-Ku Kang. A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2. In IEEE 25th International SOC Conference, SOCC 2012, Niagara Falls, NY, USA, September 12-14, 2012. pages 57-60, IEEE, 2012. [doi]

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