Mohammad Shahidzadeh, Behnam Ghavami, Steven J. E. Wilton, Lesley Shannon. Automated Verilog Assertion Generation Using Fine-Tuned LLMs with Subtask-Specific Iterative Prompting. In 26th International Symposium on Quality Electronic Design, ISQED 2025, San Francisco, CA, USA, April 23-25, 2025. pages 1-7, IEEE, 2025. [doi]
@inproceedings{ShahidzadehGWS25,
title = {Automated Verilog Assertion Generation Using Fine-Tuned LLMs with Subtask-Specific Iterative Prompting},
author = {Mohammad Shahidzadeh and Behnam Ghavami and Steven J. E. Wilton and Lesley Shannon},
year = {2025},
doi = {10.1109/ISQED65160.2025.11014349},
url = {https://doi.org/10.1109/ISQED65160.2025.11014349},
researchr = {https://researchr.org/publication/ShahidzadehGWS25},
cites = {0},
citedby = {0},
pages = {1-7},
booktitle = {26th International Symposium on Quality Electronic Design, ISQED 2025, San Francisco, CA, USA, April 23-25, 2025},
publisher = {IEEE},
isbn = {979-8-3315-0942-2},
}