Amandeep Sharan, Ashish Gupta. Hybrid Post Silicon Validation Methodology for Layerscape SoCs involving Secure Boot: Boot (Secure & Non-secure) and Kernel Integration with Randomized Test. In 16th International Workshop on Microprocessor and SOC Test and Verification, MTV 2015, Austin, TX, USA, December 3-4, 2015. pages 38-41, IEEE, 2015. [doi]
@inproceedings{SharanG15,
title = {Hybrid Post Silicon Validation Methodology for Layerscape SoCs involving Secure Boot: Boot (Secure & Non-secure) and Kernel Integration with Randomized Test},
author = {Amandeep Sharan and Ashish Gupta},
year = {2015},
doi = {10.1109/MTV.2015.16},
url = {http://doi.ieeecomputersociety.org/10.1109/MTV.2015.16},
researchr = {https://researchr.org/publication/SharanG15},
cites = {0},
citedby = {0},
pages = {38-41},
booktitle = {16th International Workshop on Microprocessor and SOC Test and Verification, MTV 2015, Austin, TX, USA, December 3-4, 2015},
publisher = {IEEE},
isbn = {978-1-5090-0885-8},
}