EJ-FAT Joint ESnet JLab FPGA Accelerated Transport Load Balancer - researchr publication authors

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Stacey Sheldon, Yatish Kumar, Michael Goodrich, Graham Heyes. EJ-FAT Joint ESnet JLab FPGA Accelerated Transport Load Balancer. In IEEE/ACM International Workshop on Innovating the Network for Data-Intensive Science, INDIS@SC 2022, Dallas, TX, USA, November 13-18, 2022. pages 32-40, IEEE, 2022. [doi]

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