An efficient VLSI architecture of VLD for AVS HDTV decoder - researchr publication related

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Bin Sheng, Wen Gao, Don Xie, Di Wu. An efficient VLSI architecture of VLD for AVS HDTV decoder. IEEE Trans. Consumer Electronics, 52(2):696-701, 2006. [doi]

The following publications are possibly variants of this publication:

An efficient VLSI architecture for CBAC of AVS HDTV decoderJunhao Zheng, Wen Gao, David Wu, Don Xie. spic, 24(4):324-332, 2009. [doi]

An Efficient VLSI Architecture for Motion Compensation of AVS HDTV DecoderJunhao Zheng, Lei Deng, Peng Zhang, Don Xie. jcst, 21(3):370-377, 2006. [doi]

A high speed and efficient architecture of VLD for AVS HD video decoderYutong Liu, Zhenqiang Yang, Huizhu Jia, Don Xie. pcs 2012: 377-380 [doi]

A flexible VLSI architecture of transport processor for an AVS HDTV decoder SoCZhenrui Zhang, Di Wu, Peng Zhang, Don Xie, Wen Gao. tce, 52(4):1427-1432, 2006. [doi]

A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV DecoderJunhao Zheng, Di Wu, Lei Deng, Don Xie, Wen Gao. pcm 2006: 424-431 [doi]

An AVS HDTV video decoder architecture employing efficient HW/SW partitioningHuizhu Jia, Peng Zhang, Don Xie, Wen Gao. tce, 52(4):1447-1453, 2006. [doi]

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