Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders

Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu. Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders. IEICE Transactions, 91-D(9):2300-2311, 2008. [doi]

@article{ShiehWW08,
  title = {Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders},
  author = {Ming-Der Shieh and Tai-Ping Wang and Chien-Ming Wu},
  year = {2008},
  doi = {10.1093/ietisy/e91-d.9.2300},
  url = {http://dx.doi.org/10.1093/ietisy/e91-d.9.2300},
  tags = {memory management},
  researchr = {https://researchr.org/publication/ShiehWW08},
  cites = {0},
  citedby = {0},
  journal = {IEICE Transactions},
  volume = {91-D},
  number = {9},
  pages = {2300-2311},
}