Microarchitectural-level statistical timing models for near-threshold circuit design

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera. Microarchitectural-level statistical timing models for near-threshold circuit design. In The 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, January 19-22, 2015. pages 87-93, IEEE, 2015. [doi]

Authors

Jun Shiomi

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Tohru Ishihara

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Hidetoshi Onodera

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