Rahul Shrestha. High-speed and low-power VLSI-architecture for inexact speculative adder. In 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, April 24-27, 2017. pages 1-4, IEEE, 2017. [doi]
@inproceedings{Shrestha17, title = {High-speed and low-power VLSI-architecture for inexact speculative adder}, author = {Rahul Shrestha}, year = {2017}, doi = {10.1109/VLSI-DAT.2017.7939644}, url = {https://doi.org/10.1109/VLSI-DAT.2017.7939644}, researchr = {https://researchr.org/publication/Shrestha17}, cites = {0}, citedby = {0}, pages = {1-4}, booktitle = {2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, April 24-27, 2017}, publisher = {IEEE}, isbn = {978-1-5090-3969-2}, }