FPGA Implementation of AES Co-processor in Counter Mode

Balwinder Singh, Harpreet Kaur, Himanshu Monga. FPGA Implementation of AES Co-processor in Counter Mode. In Vinu V. Das, R. Vijayakumar, Narayan C. Debnath, Janahanlal Stephen, Natarajan Meghanathan, Suresh Sankaranarayanan, P. M. Thankachan, Ford Lumban Gaol, Nessy Thankachan, editors, Information Processing and Management - International Conference on Recent Trends in Business Administration and Information Processing, BAIP 2010, Trivandrum, Kerala, India, March 26-27, 2010. Proceedings. Volume 70 of Communications in Computer and Information Science, pages 491-496, Springer, 2010. [doi]

@inproceedings{SinghKM10-1,
  title = {FPGA Implementation of AES Co-processor in Counter Mode},
  author = {Balwinder Singh and Harpreet Kaur and Himanshu Monga},
  year = {2010},
  doi = {10.1007/978-3-642-12214-9_85},
  url = {http://dx.doi.org/10.1007/978-3-642-12214-9_85},
  researchr = {https://researchr.org/publication/SinghKM10-1},
  cites = {0},
  citedby = {0},
  pages = {491-496},
  booktitle = {Information Processing and Management - International Conference on Recent Trends in Business Administration and Information Processing, BAIP 2010, Trivandrum, Kerala, India, March 26-27, 2010. Proceedings},
  editor = {Vinu V. Das and R. Vijayakumar and Narayan C. Debnath and Janahanlal Stephen and Natarajan Meghanathan and Suresh Sankaranarayanan and P. M. Thankachan and Ford Lumban Gaol and Nessy Thankachan},
  volume = {70},
  series = {Communications in Computer and Information Science},
  publisher = {Springer},
  isbn = {978-3-642-12213-2},
}