High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA

Panu Sjovall, Vili Viitamaki, Jarno Vanne, Timo D. Hämäläinen. High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA. In 2017 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2017, New Orleans, LA, USA, March 5-9, 2017. pages 1547-1551, IEEE, 2017. [doi]

@inproceedings{SjovallVVH17,
  title = {High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA},
  author = {Panu Sjovall and Vili Viitamaki and Jarno Vanne and Timo D. Hämäläinen},
  year = {2017},
  doi = {10.1109/ICASSP.2017.7952416},
  url = {https://doi.org/10.1109/ICASSP.2017.7952416},
  researchr = {https://researchr.org/publication/SjovallVVH17},
  cites = {0},
  citedby = {0},
  pages = {1547-1551},
  booktitle = {2017 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2017, New Orleans, LA, USA, March 5-9, 2017},
  publisher = {IEEE},
  isbn = {978-1-5090-4117-6},
}