Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jaewook Lee, Uksong Kang, Young-Soo Sohn, Jung Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin. 18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. pages 316-317, IEEE, 2016. [doi]
@inproceedings{SohnYOOSPSJSRYJ16,
title = {18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution},
author = {Kyomin Sohn and Won-Joo Yun and Reum Oh and Chi Sung Oh and Seong-Young Seo and Min-Sang Park and Dong-Hak Shin and Won-Chang Jung and Sang-Hoon Shin and Je-Min Ryu and Hye-Seung Yu and Jae-Hun Jung and Kyung-Woo Nam and Seouk-Kyu Choi and Jaewook Lee and Uksong Kang and Young-Soo Sohn and Jung Hwan Choi and Chi-Wook Kim and Seong-Jin Jang and Gyo-Young Jin},
year = {2016},
doi = {10.1109/ISSCC.2016.7418034},
url = {http://dx.doi.org/10.1109/ISSCC.2016.7418034},
researchr = {https://researchr.org/publication/SohnYOOSPSJSRYJ16},
cites = {0},
citedby = {0},
pages = {316-317},
booktitle = {2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016},
publisher = {IEEE},
isbn = {978-1-4673-9467-3},
}