Y.-S. Son, J. W. Na. A New Logic Transformation Method for Both Low Power and High Testability. In Enrico Macii, Odysseas G. Koufopavlou, Vassilis Paliouras, editors, Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings. Volume 3254 of Lecture Notes in Computer Science, pages 770-779, Springer, 2004. [doi]
@inproceedings{SonN04,
title = {A New Logic Transformation Method for Both Low Power and High Testability},
author = {Y.-S. Son and J. W. Na},
year = {2004},
url = {http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=3254&spage=770},
tags = {testing, logic, transformation},
researchr = {https://researchr.org/publication/SonN04},
cites = {0},
citedby = {0},
pages = {770-779},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings},
editor = {Enrico Macii and Odysseas G. Koufopavlou and Vassilis Paliouras},
volume = {3254},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {3-540-23095-5},
}