Ericles Rodrigues Sousa, Luis Meloni. An Analytical Model Proposed for Evaluating Efficiency of Partitioning Code in Hybrid Architectures Based on DSP and FPGA. In Parimala Thulasiraman, Laurence Tianruo Yang, Qiwen Pan, Xingang Liu, Yaw-Chung Chen, Yo-Ping Huang, Lin-Huang Chang, Che-Lun Hung, Che-Rung Lee, Justin Y. Shi, Ying Zhang, editors, 13th IEEE International Conference on High Performance Computing & Communication, HPCC 2011, Banff, Alberta, Canada, September 2-4, 2011. pages 493-499, IEEE, 2011. [doi]
@inproceedings{SousaM11,
title = {An Analytical Model Proposed for Evaluating Efficiency of Partitioning Code in Hybrid Architectures Based on DSP and FPGA},
author = {Ericles Rodrigues Sousa and Luis Meloni},
year = {2011},
doi = {10.1109/HPCC.2011.70},
url = {http://dx.doi.org/10.1109/HPCC.2011.70},
researchr = {https://researchr.org/publication/SousaM11},
cites = {0},
citedby = {0},
pages = {493-499},
booktitle = {13th IEEE International Conference on High Performance Computing & Communication, HPCC 2011, Banff, Alberta, Canada, September 2-4, 2011},
editor = {Parimala Thulasiraman and Laurence Tianruo Yang and Qiwen Pan and Xingang Liu and Yaw-Chung Chen and Yo-Ping Huang and Lin-Huang Chang and Che-Lun Hung and Che-Rung Lee and Justin Y. Shi and Ying Zhang},
publisher = {IEEE},
isbn = {978-1-4577-1564-8},
}