Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing

Sharanyan Srikanthan, Sandhya Dwarkadas, Kai Shen. Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing. In Ajay Gulati, Hakim Weatherspoon, editors, 2016 USENIX Annual Technical Conference, USENIX ATC 2016, Denver, CO, USA, June 22-24, 2016. pages 323-336, USENIX Association, 2016. [doi]

@inproceedings{SrikanthanDS16,
  title = {Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing},
  author = {Sharanyan Srikanthan and Sandhya Dwarkadas and Kai Shen},
  year = {2016},
  url = {https://www.usenix.org/conference/atc16/technical-sessions/presentation/srikanthan},
  researchr = {https://researchr.org/publication/SrikanthanDS16},
  cites = {0},
  citedby = {0},
  pages = {323-336},
  booktitle = {2016 USENIX Annual Technical Conference, USENIX ATC 2016, Denver, CO, USA, June 22-24, 2016},
  editor = {Ajay Gulati and Hakim Weatherspoon},
  publisher = {USENIX Association},
}