Jian-Wei Su, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang. 8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. IEEE Trans. Circuits Syst. II Express Briefs, 71(4):2304-2308, April 2024. [doi]
@article{SuLWCLCHRHCMLSLCHLLHTC24,
title = {8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips},
author = {Jian-Wei Su and Pei-Jung Lu and Ping-Chun Wu and Yen-Chi Chou and Ta-Wei Liu and Yen-Lin Chung and Li-Yang Hung and Jin-Sheng Ren and Wei-Hsing Huang and Chih-Han Chien and Peng-I Mei and Sih-Han Li and Shyh-Shyuan Sheu and Wei-Chung Lo and Shih-Chieh Chang and Hao-Chiao Hong and Chung-Chuan Lo and Ren-Shuo Liu and Chih-Cheng Hsieh and Kea-Tiong Tang and Meng-Fan Chang},
year = {2024},
month = {April},
doi = {10.1109/TCSII.2023.3331375},
url = {https://doi.org/10.1109/TCSII.2023.3331375},
researchr = {https://researchr.org/publication/SuLWCLCHRHCMLSLCHLLHTC24},
cites = {0},
citedby = {0},
journal = {IEEE Trans. Circuits Syst. II Express Briefs},
volume = {71},
number = {4},
pages = {2304-2308},
}