M. Sumalatha, P. V. Naganjaneyulu, K. Satya Prasad. Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising. Microprocessors and Microsystems, 71, 2019. [doi]
@article{SumalathaNP19,
title = {Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising},
author = {M. Sumalatha and P. V. Naganjaneyulu and K. Satya Prasad},
year = {2019},
doi = {10.1016/j.micpro.2019.102883},
url = {https://doi.org/10.1016/j.micpro.2019.102883},
researchr = {https://researchr.org/publication/SumalathaNP19},
cites = {0},
citedby = {0},
journal = {Microprocessors and Microsystems},
volume = {71},
}