Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa. A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit. In 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013. pages 320-321, IEEE, 2013. [doi]
@inproceedings{TachibanaHTSKKSNSYU13,
title = {A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit},
author = {Fumihiko Tachibana and Osamu Hirabayashi and Yasuhisa Takeyama and Miyako Shizuno and Atsushi Kawasumi and Keiichi Kushida and Azuma Suzuki and Yusuke Niki and Shinichi Sasaki and Tomoaki Yabe and Yasuo Unekawa},
year = {2013},
doi = {10.1109/ISSCC.2013.6487752},
url = {http://dx.doi.org/10.1109/ISSCC.2013.6487752},
researchr = {https://researchr.org/publication/TachibanaHTSKKSNSYU13},
cites = {0},
citedby = {0},
pages = {320-321},
booktitle = {2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4515-6},
}