Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo. A Model of Implementable SMT Processor on FPGA. In Hamid R. Arabnia, editor, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, PDPTA 2006, Las Vegas, Nevada, USA, June 26-29, 2006, Volume 2. pages 909-915, CSREA Press, 2006.
@inproceedings{TateOSSUAWNN06,
title = {A Model of Implementable SMT Processor on FPGA},
author = {Ippei Tate and Yoshiyasu Ogasawara and Mikiko Sato and Koichi Sasada and Kaname Uchikura and Kazunari Asano and Satoshi Watanabe and Mitaro Namiki and Hironori Nakajo},
year = {2006},
tags = {modeling, process modeling},
researchr = {https://researchr.org/publication/TateOSSUAWNN06},
cites = {0},
citedby = {0},
pages = {909-915},
booktitle = {Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, PDPTA 2006, Las Vegas, Nevada, USA, June 26-29, 2006, Volume 2},
editor = {Hamid R. Arabnia},
publisher = {CSREA Press},
isbn = {1-932415-87-4},
}