Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays

Muhammad Usman, Milos D. Ercegovac, Jeong-A Lee. Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays. VLSI Signal Processing, 95(7):777-796, July 2023. [doi]

@article{UsmanEL23,
  title = {Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays},
  author = {Muhammad Usman and Milos D. Ercegovac and Jeong-A Lee},
  year = {2023},
  month = {July},
  doi = {10.1007/s11265-023-01856-w},
  url = {https://doi.org/10.1007/s11265-023-01856-w},
  researchr = {https://researchr.org/publication/UsmanEL23},
  cites = {0},
  citedby = {0},
  journal = {VLSI Signal Processing},
  volume = {95},
  number = {7},
  pages = {777-796},
}