RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking

Vida Vakilotojar, Peter A. Beerel. RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking. In Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997. pages 181-188, IEEE, 1997. [doi]

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