Suhas K. Vittal, Moinuddin Qureshi. BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism. In IEEE International Symposium on High Performance Computer Architecture, HPCA 2026, Sydney, Australia, January 31 - Feb. 4, 2026. pages 1-15, IEEE, 2026. [doi]
@inproceedings{VittalQ26,
title = {BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism},
author = {Suhas K. Vittal and Moinuddin Qureshi},
year = {2026},
doi = {10.1109/HPCA68181.2026.11408565},
url = {https://doi.org/10.1109/HPCA68181.2026.11408565},
researchr = {https://researchr.org/publication/VittalQ26},
cites = {0},
citedby = {0},
pages = {1-15},
booktitle = {IEEE International Symposium on High Performance Computer Architecture, HPCA 2026, Sydney, Australia, January 31 - Feb. 4, 2026},
publisher = {IEEE},
isbn = {979-8-3315-9302-5},
}