A Low-Noise Analog Frontend with Large PD Capacitance Tolerance in 65-nm CMOS for Optical Receivers

Jingbo Wang, Tonghui Wang, Xiao Yang, Hong Zhang. A Low-Noise Analog Frontend with Large PD Capacitance Tolerance in 65-nm CMOS for Optical Receivers. In 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021, Zhuhai, China, November 24-26, 2021. pages 86-87, IEEE, 2021. [doi]

@inproceedings{WangWYZ21-5,
  title = {A Low-Noise Analog Frontend with Large PD Capacitance Tolerance in 65-nm CMOS for Optical Receivers},
  author = {Jingbo Wang and Tonghui Wang and Xiao Yang and Hong Zhang},
  year = {2021},
  doi = {10.1109/ICTA53157.2021.9661603},
  url = {https://doi.org/10.1109/ICTA53157.2021.9661603},
  researchr = {https://researchr.org/publication/WangWYZ21-5},
  cites = {0},
  citedby = {0},
  pages = {86-87},
  booktitle = {2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021, Zhuhai, China, November 24-26, 2021},
  publisher = {IEEE},
  isbn = {978-1-6654-1747-1},
}