Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities

Qian Wang, Sotirios G. Ziavras. Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities. In 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 99), 23-25 June 1999, Fremantle, Australia. pages 222-229, IEEE Computer Society, 1999. [doi]

@inproceedings{WangZ99:3,
  title = {Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities},
  author = {Qian Wang and Sotirios G. Ziavras},
  year = {1999},
  url = {http://csdl.computer.org/comp/proceedings/ispan/1999/0231/00/02310222abs.htm},
  researchr = {https://researchr.org/publication/WangZ99%3A3},
  cites = {0},
  citedby = {0},
  pages = {222-229},
  booktitle = {1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN  99), 23-25 June 1999, Fremantle, Australia},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-0231-8},
}