Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai. A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. VLSI Signal Processing, 33(1-2):191-197, 2003. [doi]
@article{WuCSG03,
title = {A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems},
author = {Xingjun Wu and Hongyi Chen and Yihe Sun and Weixin Gai},
year = {2003},
doi = {10.1023/A:1021110405895},
url = {http://dx.doi.org/10.1023/A:1021110405895},
tags = {architecture},
researchr = {https://researchr.org/publication/WuCSG03},
cites = {0},
citedby = {0},
journal = {VLSI Signal Processing},
volume = {33},
number = {1-2},
pages = {191-197},
}