Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang 0001. A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation. IEEE Trans. Circuits Syst. II Express Briefs, 70(6):1816-1820, June 2023. [doi]
@article{XiaoCQSLWW23,
title = {A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation},
author = {Kanglin Xiao and Xiaoxin Cui and Xin Qiao and Jiahao Song and Haoyang Luo and Xin'an Wang and Yuan Wang 0001},
year = {2023},
month = {June},
doi = {10.1109/TCSII.2023.3234620},
url = {https://doi.org/10.1109/TCSII.2023.3234620},
researchr = {https://researchr.org/publication/XiaoCQSLWW23},
cites = {0},
citedby = {0},
journal = {IEEE Trans. Circuits Syst. II Express Briefs},
volume = {70},
number = {6},
pages = {1816-1820},
}