COSY: An Energy-Efficient Hardware Architecture for Deep Convolutional Neural Networks Based on Systolic Array - researchr publication authors

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Chen Xin, Qiang Chen, Miren Tian, Mohan Ji, Chenglong Zou, Xin'an Wang, Bo Wang. COSY: An Energy-Efficient Hardware Architecture for Deep Convolutional Neural Networks Based on Systolic Array. In 23rd IEEE International Conference on Parallel and Distributed Systems, ICPADS 2017, Shenzhen, China, December 15-17, 2017. pages 180-189, IEEE Computer Society, 2017. [doi]

This author has not been identified. Look up 'Chen Xin' in GoogleThis author has not been identified. Look up 'Qiang Chen' in GoogleThis author has not been identified. Look up 'Miren Tian' in GoogleThis author has not been identified. Look up 'Mohan Ji' in GoogleThis author has not been identified. Look up 'Chenglong Zou' in GoogleThis author has not been identified. Look up 'Xin'an Wang' in GoogleThis author has not been identified. Look up 'Bo Wang' in Google

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