FPGA-Based Annealing Processor with Time-Division Multiplexing

Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki. FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Transactions, 102-D(12):2295-2305, 2019. [doi]

@article{YamamotoIAMT19,
  title = {FPGA-Based Annealing Processor with Time-Division Multiplexing},
  author = {Kasho Yamamoto and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
  year = {2019},
  url = {http://search.ieice.org/bin/summary.php?id=e102-d_12_2295},
  researchr = {https://researchr.org/publication/YamamotoIAMT19},
  cites = {0},
  citedby = {0},
  journal = {IEICE Transactions},
  volume = {102-D},
  number = {12},
  pages = {2295-2305},
}