Lane Shared Bit-Pragmatic Deep Neural Network Computing Architecture and Circuit

Shaofei Yang, Longjun Liu, Yingxiang Li, Xinxin Li, Hongbin Sun 0001, Nanning Zheng. Lane Shared Bit-Pragmatic Deep Neural Network Computing Architecture and Circuit. IEEE Trans. Circuits Syst. II Express Briefs, 68-II(1):486-490, 2021. [doi]

@article{YangLLLSZ21,
  title = {Lane Shared Bit-Pragmatic Deep Neural Network Computing Architecture and Circuit},
  author = {Shaofei Yang and Longjun Liu and Yingxiang Li and Xinxin Li and Hongbin Sun 0001 and Nanning Zheng},
  year = {2021},
  doi = {10.1109/TCSII.2020.3007983},
  url = {https://doi.org/10.1109/TCSII.2020.3007983},
  researchr = {https://researchr.org/publication/YangLLLSZ21},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. Circuits Syst. II Express Briefs},
  volume = {68-II},
  number = {1},
  pages = {486-490},
}