VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity

Lei Yang, Hui Liu, C.-J. Richard Shi. VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity. In Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November - 2 December 2005. pages 6, IEEE, 2005. [doi]

@inproceedings{YangLS05-0,
  title = {VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity},
  author = {Lei Yang and Hui Liu and C.-J. Richard Shi},
  year = {2005},
  doi = {10.1109/GLOCOM.2005.1577854},
  url = {http://dx.doi.org/10.1109/GLOCOM.2005.1577854},
  researchr = {https://researchr.org/publication/YangLS05-0},
  cites = {0},
  citedby = {0},
  pages = {6},
  booktitle = {Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November - 2 December 2005},
  publisher = {IEEE},
  isbn = {0-7803-9414-3},
}