Architecture and performance models for scalable IP lookup engines on FPGA - researchr publication authors

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Yi-Hua E. Yang, Yun Qu, Swapnil Haria, Viktor K. Prasanna. Architecture and performance models for scalable IP lookup engines on FPGA. In IEEE 14th International Conference on High Performance Switching and Routing, HPSR 2013, Taipei, Taiwan, July 8-11, 2013. pages 156-163, IEEE, 2013. [doi]

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