Haruyoshi Yonekawa, Hiroki Nakahara. On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA. In 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPS Workshops 2017, Orlando / Buena Vista, FL, USA, May 29 - June 2, 2017. pages 98-105, IEEE Computer Society, 2017. [doi]
@inproceedings{YonekawaN17, title = {On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA}, author = {Haruyoshi Yonekawa and Hiroki Nakahara}, year = {2017}, doi = {10.1109/IPDPSW.2017.95}, url = {https://doi.org/10.1109/IPDPSW.2017.95}, researchr = {https://researchr.org/publication/YonekawaN17}, cites = {0}, citedby = {0}, pages = {98-105}, booktitle = {2017 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPS Workshops 2017, Orlando / Buena Vista, FL, USA, May 29 - June 2, 2017}, publisher = {IEEE Computer Society}, isbn = {978-1-5386-3408-0}, }