Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure - researchr publication authors

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Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto. Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. IEICE Transactions, 95-C(10):1675-1681, 2012. [doi]

This author has not been identified. Look up 'Shusuke Yoshimoto' in GoogleThis author has not been identified. Look up 'Takuro Amashita' in GoogleThis author has not been identified. Look up 'Shunsuke Okumura' in GoogleThis author has not been identified. Look up 'Hiroshi Kawaguchi' in GoogleThis author has not been identified. Look up 'Masahiko Yoshimoto' in Google

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