SoC Memory Test Optimization using NXP MTR Solutions

Rodrigo Zeli, Reinaldo Silveira, Qadeer Qureshi. SoC Memory Test Optimization using NXP MTR Solutions. In IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019. pages 1-5, IEEE, 2019. [doi]

@inproceedings{ZeliSQ19,
  title = {SoC Memory Test Optimization using NXP MTR Solutions},
  author = {Rodrigo Zeli and Reinaldo Silveira and Qadeer Qureshi},
  year = {2019},
  doi = {10.1109/LATW.2019.8704566},
  url = {https://doi.org/10.1109/LATW.2019.8704566},
  researchr = {https://researchr.org/publication/ZeliSQ19},
  cites = {0},
  citedby = {0},
  pages = {1-5},
  booktitle = {IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-1756-0},
}