A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS

Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto. A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS. IEICE Transactions, 96-A(12):2623-2632, 2013. [doi]

@article{ZhaoCPZG13,
  title = {A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS},
  author = {Xiongxin Zhao and Zhixiang Chen and Xiao Peng and Dajiang Zhou and Satoshi Goto},
  year = {2013},
  url = {http://search.ieice.org/bin/summary.php?id=e96-a_12_2623},
  researchr = {https://researchr.org/publication/ZhaoCPZG13},
  cites = {0},
  citedby = {0},
  journal = {IEICE Transactions},
  volume = {96-A},
  number = {12},
  pages = {2623-2632},
}