Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo. Geyser-2: The second prototype CPU with fine-grained run-time power gating. In Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011. pages 87-88, IEEE, 2011. [doi]
@inproceedings{ZhaoISKSKAKHUMUKNTNK11,
title = {Geyser-2: The second prototype CPU with fine-grained run-time power gating},
author = {Lei Zhao and Daisuke Ikebuchi and Yoshiki Saito and M. Kamata and Naomi Seki and Yu Kojima and Hideharu Amano and Satoshi Koyama and Tatsunori Hashida and Y. Umahashi and D. Masuda and Kimiyoshi Usami and Keiji Kimura and Mitaro Namiki and Seidai Takeda and Hiroshi Nakamura and Masaaki Kondo},
year = {2011},
doi = {10.1109/ASPDAC.2011.5722310},
url = {http://dx.doi.org/10.1109/ASPDAC.2011.5722310},
researchr = {https://researchr.org/publication/ZhaoISKSKAKHUMUKNTNK11},
cites = {0},
citedby = {0},
pages = {87-88},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011},
publisher = {IEEE},
isbn = {978-1-4244-7516-2},
}