Advanced DFT Clock Control Architectures with Agile Development for Chisel-Based High Performance RISC-V Processors

Qi Zhao, Huibin Tao, Zhiheng He, Ruining Feng. Advanced DFT Clock Control Architectures with Agile Development for Chisel-Based High Performance RISC-V Processors. In IEEE International Test Conference in Asia, ITC-Asia 2024, Changsha, China, August 18-20, 2024. pages 1-6, IEEE, 2024. [doi]

@inproceedings{ZhaoTHF24,
  title = {Advanced DFT Clock Control Architectures with Agile Development for Chisel-Based High Performance RISC-V Processors},
  author = {Qi Zhao and Huibin Tao and Zhiheng He and Ruining Feng},
  year = {2024},
  doi = {10.1109/ITC-Asia62534.2024.10661311},
  url = {https://doi.org/10.1109/ITC-Asia62534.2024.10661311},
  researchr = {https://researchr.org/publication/ZhaoTHF24},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {IEEE International Test Conference in Asia, ITC-Asia 2024, Changsha, China, August 18-20, 2024},
  publisher = {IEEE},
  isbn = {979-8-3315-4033-3},
}