An efficient page-level FTL to optimize address translation in flash memory

You Zhou, Fei Wu, Ping Huang, Xubin He, Changsheng Xie, Jian Zhou. An efficient page-level FTL to optimize address translation in flash memory. In Laurent Réveillère, Tim Harris 0001, Maurice Herlihy, editors, Proceedings of the Tenth European Conference on Computer Systems, EuroSys 2015, Bordeaux, France, April 21-24, 2015. pages 12, ACM, 2015. [doi]

@inproceedings{ZhouWHHXZ15,
  title = {An efficient page-level FTL to optimize address translation in flash memory},
  author = {You Zhou and Fei Wu and Ping Huang and Xubin He and Changsheng Xie and Jian Zhou},
  year = {2015},
  doi = {10.1145/2741948.2741949},
  url = {http://doi.acm.org/10.1145/2741948.2741949},
  researchr = {https://researchr.org/publication/ZhouWHHXZ15},
  cites = {0},
  citedby = {0},
  pages = {12},
  booktitle = {Proceedings of the Tenth European Conference on Computer Systems, EuroSys 2015, Bordeaux, France, April 21-24, 2015},
  editor = {Laurent Réveillère and Tim Harris 0001 and Maurice Herlihy},
  publisher = {ACM},
  isbn = {978-1-4503-3238-5},
}