2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS

Yan Zhu 0001, Chi-Hang Chan, Zi-Hao Zheng, Cheng Li 0010, Jianyu Zhong, Rui P. Martins. 2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS. IEEE Trans. on Circuits and Systems, 65-I(11):3606-3616, 2018. [doi]

@article{ZhuCZLZM18,
  title = {2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS},
  author = {Yan Zhu 0001 and Chi-Hang Chan and Zi-Hao Zheng and Cheng Li 0010 and Jianyu Zhong and Rui P. Martins},
  year = {2018},
  doi = {10.1109/TCSI.2018.2859027},
  url = {https://doi.org/10.1109/TCSI.2018.2859027},
  researchr = {https://researchr.org/publication/ZhuCZLZM18},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on Circuits and Systems},
  volume = {65-I},
  number = {11},
  pages = {3606-3616},
}