Challenges and Solutions in Post-Silicon Validation of High-end Processors (Invited Tutorial)

Avi Ziv. Challenges and Solutions in Post-Silicon Validation of High-end Processors (Invited Tutorial). In Clark W. Barrett, Jin Yang, editors, 2019 Formal Methods in Computer Aided Design, FMCAD 2019, San Jose, CA, USA, October 22-25, 2019. pages 1, IEEE, 2019. [doi]

@inproceedings{Ziv19,
  title = {Challenges and Solutions in Post-Silicon Validation of High-end Processors (Invited Tutorial)},
  author = {Avi Ziv},
  year = {2019},
  doi = {10.23919/FMCAD.2019.8894258},
  url = {https://doi.org/10.23919/FMCAD.2019.8894258},
  researchr = {https://researchr.org/publication/Ziv19},
  cites = {0},
  citedby = {0},
  pages = {1},
  booktitle = {2019 Formal Methods in Computer Aided Design, FMCAD 2019, San Jose, CA, USA, October 22-25, 2019},
  editor = {Clark W. Barrett and Jin Yang},
  publisher = {IEEE},
  isbn = {978-0-9835678-9-9},
}