Sudarshan Bahukudumbi. Wafer-Level Testing and Test Planning for Integrated Circuits. PhD thesis, Duke University, Durham, NC, USA, 2008. [doi]
@phdthesis{basesearch-1567,
title = {Wafer-Level Testing and Test Planning for Integrated Circuits},
author = {Sudarshan Bahukudumbi},
year = {2008},
url = {https://www.base-search.net/Record/eb966814f9a532a21ef1516b59af1d9c190dccb6107572d6484245944bf5d20d},
note = {base-search.net (ftdukeunivdsp:oai:dukespace.lib.duke.edu:10161/701)},
researchr = {https://researchr.org/publication/basesearch-1567},
cites = {0},
citedby = {0},
school = {Duke University, Durham, NC, USA},
}