An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices

Carl Edward Gray. An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. PhD thesis, Georgia Institute of Technology, Atlanta, GA, USA, 2012. [doi]

@phdthesis{basesearch-4007,
  title = {An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices},
  author = {Carl Edward Gray},
  year = {2012},
  url = {https://www.base-search.net/Record/dc47490405869fc6ce568011484f44e789222e3fc5a89c518cd23d89776ceccc},
  note = {base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/44858)},
  researchr = {https://researchr.org/publication/basesearch-4007},
  cites = {0},
  citedby = {0},
  school = {Georgia Institute of Technology, Atlanta, GA, USA},
}