Björn Osterloh - researchr alias

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Viewing Publication 1 - 7 from 7

2011

AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unitHolger Michel, Frank Bubenhagen, Björn Fiethe, Harald Michalik, Björn Osterloh, Wayne Sullivan, Alex Wishart, Jørgen Ilstad, Sandi Habinc. ahs 2011: 227-233 [doi]

2010

Architecture verification of the SoCWire NoC approach for safe dynamic partial reconfiguration in space applicationsBjörn Osterloh, Harald Michalik, Björn Fiethe, Frank Bubenhagen. ahs 2010: 1-8 [doi]

2009

SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAsBjörn Osterloh, Harald Michalik, Björn Fiethe. arcs 2009: 50-59 [doi]

Dynamic Partial Reconfiguration in Space ApplicationsBjörn Osterloh, Harald Michalik, Sandi Habinc, Björn Fiethe. ahs 2009: 336-343 [doi]

2008

SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space ApplicationsBjörn Osterloh, Harald Michalik, Björn Fiethe, Karel Kotarowski. ahs 2008: 51-56 [doi]

2007

Reconfigurable system-on-chip data processing units for space imaging instrumentsBjörn Fiethe, Harald Michalik, C. Dierker, Björn Osterloh, G. Zhou. date 2007: 977-982 [doi]

Enhancements of reconfigurable System-on-Chip Data Processing Units for Space ApplicationBjörn Osterloh, Harald Michalik, Björn Fiethe, F. Bubenhagen. ahs 2007: 258-262 [doi]

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