Abstract is missing.
- Keynote address: Challenges of digital consumer and mobile SoC s: more Moore possible?Tohru Furuyama. 1 [doi]
- Keynote address: Was Darwin wrong? Has design evolution stopped at the RTL level... or will software and custom processors (or system-level design) extend Moore s law?Alan Naumann. 2 [doi]
- ATLAS: a chip-multiprocessor with transactional memory supportNjuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun. 3-8 [doi]
- A dynamically adaptive DSP for heterogeneous reconfigurable platformsFabio Campi, Antonio Deledda, Matteo Pizzotti, Luca Ciccarelli, Pier Luigi Rolandi, Claudio Mucci, Andrea Lodi 0002, Arseni Vitkovski, Luca Vanzolini. 9-14 [doi]
- An 0.9 × 1.2 , low power, energy-harvesting system with custom multi-channel communication interfacePhillip Stanley-Marbell, Diana Marculescu. 15-20 [doi]
- Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radioZhuan Ye, John Grosspietsch, Gokhan Memik. 21-26 [doi]
- A non-intrusive isolation approach for soft coresOzgur Sinanoglu, Tsvetomir Petrov. 27-32 [doi]
- Unknown blocking scheme for low control data volume and high observabilitySeongmoon Wang, Wenlong Wei, Srimat T. Chakradhar. 33-38 [doi]
- Test cost reduction for SoC using a combined approach to test data compression and test schedulingQuming Zhou, Kedarnath J. Balakrishnan. 39-44 [doi]
- High-level test synthesis for delay fault testabilitySying-Jyan Wang, Tung-Hua Yeh. 45-50 [doi]
- Bus access optimisation for FlexRay-based distributed embedded systemsTraian Pop, Paul Pop, Petru Eles, Zebo Peng. 51-56 [doi]
- A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessorsNadathur Satish, Kaushik Ravindran, Kurt Keutzer. 57-62 [doi]
- Design closure driven delay relaxation based on convex cost network flowChuan Lin, Aiguo Xie, Hai Zhou. 63-68 [doi]
- Simulation-based reusable posynomial models for MOS transistor parametersVarun Aggarwal, Una-May O Reilly. 69-74 [doi]
- Trade-off design of analog circuits using goal attainment and Wave Front sequential quadratic programmingDaniel Mueller, Helmut E. Graeb, Ulf Schlichtmann. 75-80 [doi]
- An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selectionTom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen. 81-86 [doi]
- Interactive presentation: A coefficient optimization and architecture selection tool for SigmaDelta modulators in MATLABÖmer Yetik, Orkun Saglamdemir, Selçuk Talay, Günhan Dündar. 87-92 [doi]
- Synthesis of task and message activation models in real-time distributed automotive systemsWei Zheng, Marco Di Natale, Claudio Pinello, Paolo Giusto, Alberto L. Sangiovanni-Vincentelli. 93-98 [doi]
- An ILP formulation for system-level application mapping on network processor architecturesChristopher Ostler, Karam S. Chatha. 99-104 [doi]
- A smooth refinement flow for co-designing HW and SW threadsPaolo Destro, Franco Fummi, Graziano Pravadelli. 105-110 [doi]
- Speeding up SystemC simulation through process splittingYoussef N. Naguib, Rafik S. Guindi. 111-116 [doi]
- Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chipAkash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal. 117-122 [doi]
- Hard real-time reconfiguration port schedulingFlorian Dittmann, Stefan Frank. 123-128 [doi]
- An efficient algorithm for online management of 2D area of partially reconfigurable FPGAsJin Cui, Qingxu Deng, Xiuqiang He, Zonghua Gu. 129-134 [doi]
- Improving utilization of reconfigurable resources using two dimensional compactionAhmed A. El Farag, Hatem M. El-Boghdadi, Samir I. Shaheen. 135-140 [doi]
- Low-power warp processor for power efficient high-performance embedded systemsRoman L. Lysecky. 141-146 [doi]
- Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devicesYang Qu, Juha-Pekka Soininen, Jari Nurmi. 147-152 [doi]
- Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solverMona Safar, Mohamed Shalan, M. Watheq El-Kharashi, Ashraf Salem. 153-158 [doi]
- Efficient high-performance ASIC implementation of JPEG-LS encoderMarkos Papadonikolakis, Vasilleios Pantazis, Athanasios Kakarountas. 159-164 [doi]
- Improve CAM power efficiency using decoupled match line schemeYen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan. 165-170 [doi]
- Cyclostationary feature detection on a tiled-SoCAndré B. J. Kokkeler, Gerard J. M. Smit, Thijs Krol, Jan Kuper. 171-176 [doi]
- Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filterC. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet. 177-182 [doi]
- Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithmEsra Sahin, Ilker Hamzaoglu. 183-188 [doi]
- Interactive presentation: An FPGA implementation of decision tree classificationRamanathan Narayanan, Daniel Honbo, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno. 189-194 [doi]
- Interactive presentation: Radix 4 SRT division with quotient prediction and operand scalingNishant R. Srivastava. 195-200 [doi]
- SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test schedulingZhanglei Wang, Krishnendu Chakrabarty, Seongmoon Wang. 201-206 [doi]
- Optimized integration of test compression and sharing for SOC testingAnders Larsson, Erik Larsson, Petru Eles, Zebo Peng. 207-212 [doi]
- A sophisticated memory test engine for LCD display driversOliver Spang, Hans Martin von Staudt, Michael G. Wahl. 213-218 [doi]
- Formal verification of a pervasive interconnect bus system in a high-performance microprocessorThuyen Le, Tilman Glökler, Jason Baumgartner. 219-224 [doi]
- Interactive presentation: Low cost debug architecture using lossy compression for silicon debugEhab Anis, Nicola Nicolici. 225-230 [doi]
- Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappersTomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara. 231-236 [doi]
- Microprocessors in the era of terascale integrationShekhar Borkar, Norman P. Jouppi, Per Stenström. 237-242 [doi]
- CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functionsM. Zhang, Markus Olbrich, D. Seider, M. Frerichs, H. Kinzelbach, Erich Barke. 243-248 [doi]
- A symbolic methodology for the verification of analog and mixed signal designsGhiath Al Sammane, Mohamed H. Zaki, Sofiène Tahar. 249-254 [doi]
- Efficient nonlinear distortion analysis of RF circuitsDani Tannir, Roni Khazaka. 255-260 [doi]
- Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysisJonathan Borremans, Ludwig De Locht, Piet Wambacq, Yves Rolain. 261-266 [doi]
- Interactive presentation: Optimizing analog filter designs for minimum nonlinear distortions using multisine excitationsJ. Lataire, Gerd Vandersteen, Rik Pintelon. 267-272 [doi]
- Performance analysis of complex systems by integration of dataflow graphs and compositional performance analysisSimon Schliecker, Steffen Stein, Rolf Ernst. 273-278 [doi]
- Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESLHiren D. Patel, Sandeep K. Shukla. 279-284 [doi]
- A calculator for Pareto pointsMarc Geilen, Twan Basten. 285-290 [doi]
- Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizerShuilong Huang, Huainan Ma, Zhihua Wang. 291-296 [doi]
- Interactive presentation: System level power optimization of Sigma-Delta modulatorFei Gong, Xiaobo Wu. 297-300 [doi]
- Interactive presentation: Executable system-level specification models containing UML-based behavioral patternsLeandro Soares Indrusiak, Andreas Thuy, Manfred Glesner. 301-306 [doi]
- Assessing carbon nanotube bundle interconnect for future FPGA architecturesSoumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud. 307-312 [doi]
- Two-level microprocessor-accelerator partitioningScott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid. 313-318 [doi]
- Design space exploration of partially re-configurable embedded processorsAnupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 319-324 [doi]
- Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processorHamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Maziar Goudarzi. 325-330 [doi]
- Low complexity LDPC code decoders for next generation standardsTorben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Nicola E. L Insalata, Francesco Rossi, Massimo Rovini, Luca Fanucci. 331-336 [doi]
- Non-fractional parallelism in LDPC decoder implementationsJohn Dielissen, Andries Hekstra. 337-342 [doi]
- Minimum-energy LDPC decoder for real-time mobile applicationWeihuang Wang, Gwan Choi. 343-348 [doi]
- Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architectureZahid Khan, Tughrul Arslan. 349-354 [doi]
- Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architectureClaudio Mucci, Luca Vanzolini, Fabio Campi, Mario Toma. 355-360 [doi]
- Using the inter- and intra-switch regularity in NoC switch testingMohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi. 361-366 [doi]
- Toward a scalable test methodology for 2D-mesh Network-on-ChipsKim Petersén, Johnny Öberg. 367-372 [doi]
- Remote testing and diagnosis of System-on-Chips using network management frameworksOussama Laouamri, Chouki Aktouf. 373-378 [doi]
- Fast memory footprint estimation based on maximal dependency vector calculationQubo Hu, Arnout Vandecappelle, Per Gunnar Kjeldsberg, Francky Catthoor, Martin Palkovic. 379-384 [doi]
- Mapping multi-dimensional signals into hierarchical memory organizationsHongwei Zhu, Ilie I. Luican, Florin Balasa. 385-390 [doi]
- The impact of loop unrolling on controller delay in high level synthesisSrikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda. 391-396 [doi]
- Clock-frequency assignment for multiple clock domain systems-on-a-chipScott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid. 397-402 [doi]
- Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designsSiddharth Garg, Diana Marculescu. 403-408 [doi]
- Interactive presentation: Reliability-aware system synthesisMichael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich. 409-414 [doi]
- Flexibility-oriented design methodology for reconfigurable DeltaSigma modulatorsPengbo Sun, Ying Wei, Alex Doboli. 415-420 [doi]
- Experimental validation of a tuning algorithm for high-speed filtersGianvito Matarrese, Cristoforo Marzocca, Francesco Corsi, Stefano D Amico, Andrea Baschirotto. 421-426 [doi]
- Design of high-resolution MOSFET-only pipelined ADCs with digital calibrationHamed Aminzadeh, Mohammad Danaie, Reza Lotfi. 427-432 [doi]
- A new technique for characterization of digital-to-analog converters in high-speed systemsJafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz. 433-438 [doi]
- DFM/DFY: should you trust the surgeon or the family doctor?Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki. 439-442 [doi]
- Automatic synthesis of compressor trees: reevaluating large countersAjay K. Verma, Paolo Ienne. 443-448 [doi]
- Area optimization of multi-cycle operators in high-level synthesisMaría C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida. 449-454 [doi]
- Data-flow transformations using Taylor expansion diagramsMaciej J. Ciesielski, Serkan Askar, D. Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon. 455-460 [doi]
- Automatic application specific floating-point unit generationYee Jern Chong, Sri Parameswaran. 461-466 [doi]
- Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASPMario Schölzel. 467-472 [doi]
- Applications for ubiquitous computing and communications473 [doi]
- Timing simulation of interconnected AUTOSAR software-componentsMatthias Krause, Oliver Bringmann, André Hergenhan, Gökhan Tabanoglu, Wolfgang Rosenstiel. 474-479 [doi]
- FPGA-based networking systems for high data-rate and reliable in-vehicle communicationsSergio Saponara, Esa Petri, Marco Tonarelli, Iacopo Del Corona, Luca Fanucci. 480-485 [doi]
- Low-g accelerometer fast prototyping for automotive applicationsFrancesco D Ascoli, Francesco Iozzi, Corrado Marino, Massimiliano Melani, Marco Tonarelli, Luca Fanucci, A. Giambastiani, A. Rocchi, Marco De Marinis. 486-491 [doi]
- Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508Riccardo Mariani, Gabriele Boschi, Federico Colucci. 492-497 [doi]
- Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance systemChristopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele. 498-503 [doi]
- Interactive presentation: Towards a methodology for the quantitative evaluation of automotive architecturesPatrick Popp, Marco Di Natale, Paolo Giusto, Sri Kanajan, Claudio Pinello. 504-509 [doi]
- Dynamic learning based scan chain diagnosisYu Huang. 510-515 [doi]
- Diagnosis, modeling and tolerance of scan chain hold-time violationsOzgur Sinanoglu, Philip Schremmer. 516-521 [doi]
- On test generation by input cube avoidanceIrith Pomeranz, Sudhakar M. Reddy. 522-527 [doi]
- Slow write driver faults in 65nm SRAM technology: analysis and March test solutionA. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian. 528-533 [doi]
- Interactive presentation: On power-profiling and pattern generation for power-safe scan testsV. R. Devanathan, C. P. Ravikumar, V. Kamakoti. 534-539 [doi]
- Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faultsKunal P. Ganeshpure, Sandip Kundu. 540-545 [doi]
- Temperature-aware NBTI modeling and the impact of input vector control on performance degradationYu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie. 546-551 [doi]
- A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arraysTao Xu, Krishnendu Chakrabarty. 552-557 [doi]
- Reversible circuit technology mapping from non-reversible specificationsZeljko Zilic, Katarzyna Radecka, Ali Kazamiphur. 558-563 [doi]
- Distributed power-management techniques for wireless network video systemsNicholas H. Zamora, Jung-Chun Kao, Radu Marculescu. 564-569 [doi]
- Interactive presentation: Improving the fault tolerance of nanometric PLA designsFederico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli. 570-575 [doi]
- Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuitsKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky. 576-581 [doi]
- An efficient code compression technique using application-aware bitmask and dictionary selection methodsSeok-Won Seong, Prabhat Mishra. 582-587 [doi]
- Optimizing instruction-set extensible processors under data bandwidth constraintsKubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar. 588-593 [doi]
- Resource prediction for media stream decodingJuan Hamers, Lieven Eeckhout. 594-599 [doi]
- Register pointer architecture for efficient embedded processorsJongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally. 600-605 [doi]
- Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random searchS. van Haastregt, Peter M. W. Knijnenburg. 606-611 [doi]
- Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchyAthanasios Milidonis, N. Alachiotis, V. Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis. 612-617 [doi]
- An algorithm to minimize leakage through simultaneous input vector control and circuit modificationNikhil Jayakumar, Sunil P. Khatri. 618-623 [doi]
- Understanding voltage variations in chip multiprocessors using a distributed power-delivery networkMeeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks. 624-629 [doi]
- Process variation tolerant low power DCT architectureNilanjan Banerjee, Georgios Karakonstantis, Kaushik Roy. 630-635 [doi]
- Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reductionYan Lin, Lei He. 636-641 [doi]
- Hardware scheduling support in SMP architecturesAndré C. Nácul, Francesco Regazzoni, Marcello Lajolo. 642-647 [doi]
- A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution methodTobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø. 648-653 [doi]
- Butterfly and benes-based on-chip communication networks for multiprocessor turbo decodingHazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel. 654-659 [doi]
- Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platformsSimone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto. 660-665 [doi]
- Cost-aware capacity optimization in dynamic multi-hop WSNsJukka Suhonen, Mikko Kohvakka, Mauri Kuorilehto, Marko Hännikäinen, Timo D. Hämäläinen. 666-671 [doi]
- Design methods for security and trustIngrid Verbauwhede, Patrick Schaumont. 672-677 [doi]
- Emerging solutions technology and business views for the ubiquitous communicationHeikki Huomo. 678 [doi]
- Development of on board, highly flexible, Galileo signal generator ASICLouis Baguena, Emmanuel Liégeon, Alexandra Bépoix, Jean-Marc Dusserre, Christophe Oustric, Philippe Bellocq, Vincent Heiries. 679-683 [doi]
- New safety critical radio altimeter for airbus and related design flowD. Hairion, S. Emeriau, E. Combot, M. Sarlotte. 684-688 [doi]
- Introducing new verification methods into a company s design flow: an industrial user s point of viewRobert Lissel, Joachim Gerlach, Robert Bosch GmbH. 689-694 [doi]
- Testable design for advanced serial-link transceiversMitchell Lin, Kwang-Ting (Tim) Cheng. 695-700 [doi]
- Method for reducing jitter in multi-gigahertz ATEDavid C. Keezer, Dany Minier, Patrice Ducharme. 701-706 [doi]
- Re-configuration of sub-blocks for effective application of time domain testsJens Anders, Shaji Krishnan, Guido Gronthoud. 707-712 [doi]
- An ADC-BiST scheme using sequential code analysisErdem Serkan Erdogan, Sule Ozev. 713-718 [doi]
- Interactive presentation: Boosting SER test for RF transceivers by simple DSP techniqueJerzy Dabrowski, Rashad Ramzan. 719-724 [doi]
- Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processorP. Yeung, A. Torres, P. Batra. 725-730 [doi]
- Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical modelJeanne Tongbong, Salvador Mir, Jean-Louis Carbonéro. 731-736 [doi]
- Heterogeneous systems on chip and systems in packageI. O Connor, B. Courtois, K. Chakrabarty, N. Delorme, M. Hampton, J. Hartung. 737-742 [doi]
- Engineering trust with semantic guardiansIlya Wagner, Valeria Bertacco. 743-748 [doi]
- CATS: cycle accurate transaction-driven simulation with multiple processor simulatorsDohyung Kim, Soonhoi Ha, Rajesh Gupta. 749-754 [doi]
- A one-shot configurable-cache tuner for improved energy and performanceAnn Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros. 755-760 [doi]
- Design fault directed test generation for microprocessor validationDeepak Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, David J. Lilja, Ajit Dingankar. 761-766 [doi]
- Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performanceWolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull. 767-772 [doi]
- Adaptive power management in energy harvesting systemsClemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini. 773-778 [doi]
- Stochastic modeling and optimization for robust power management in a partially observable systemQinru Qiu, Ying Tan, Qing Wu. 779-784 [doi]
- Efficient and scalable compiler-directed energy optimization for realtime applicationsPo-Kuan Huang, Soheil Ghiasi. 785-790 [doi]
- Interactive presentation: Peripheral-conscious scheduling on energy minimization for weakly hard real-time systemsLinwei Niu, Gang Quan. 791-796 [doi]
- Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoCRyo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya. 797-802 [doi]
- Instruction trace compression for rapid instruction cache simulationAndhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel. 803-808 [doi]
- Efficient code density through look-up table compressionTalal Bonny, Jörg Henkel. 809-814 [doi]
- Microarchitectural support for program code integrity monitoring in application-specific instruction set processorsYunsi Fei, Zhijie Jerry Shi. 815-820 [doi]
- Interactive presentation: Soft-core processor customization using the design of experiments paradigmDavid Sheldon, Frank Vahid, Stefano Lonardi. 821-826 [doi]
- Power supply and power management in Ubicom827 [doi]
- From algorithm to first 3.5G call in record time: a novel system design approach based on virtual prototyping and its consequences for interdisciplinary system design teamsM. Brandenburg, A. Schöllhorn, S. Heinen, Josef Eckmueller, T. Eckart. 828-830 [doi]
- Portable multimedia SoC design: a global challengeMaurizio Paganini, Georg Kimmich, Stephane Ducrey, Guilhem Caubit, Vincent Coeffe. 831-834 [doi]
- What if you could design tomorrow s system today?Neal Wingen. 835-840 [doi]
- Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETsHamidreza Hashempour, Fabrizio Lombardi. 841-846 [doi]
- Error rate reduction in DNA self-assembly by non-constant monomer concentrations and profilingB. Jang, Y-B. Kim, F. Lombardi. 847-852 [doi]
- Design and DfT of a high-speed area-efficient embedded asynchronous FIFOPaul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters. 853-858 [doi]
- Test quality analysis and improvement for an embedded asynchronous FIFOTobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters. 859-864 [doi]
- Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAsWenjing Rao, Alex Orailoglu, Ramesh Karri. 865-869 [doi]
- A multi-core debug platform for NoC-based systemsShan Tang, Qiang Xu. 870-875 [doi]
- Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS supportL. Moss, Maxime de Nanclas, Luc Filion, Sebastien Fontaine, Guy Bois, M. Aboulhamid. 876-881 [doi]
- Incremental ABV for functional validation of TL-to-RTL design refinementNicola Bombieri, Franco Fummi, Graziano Pravadelli. 882-887 [doi]
- Efficient testbench code synthesis for a hardware emulator systemIoannis Mavroidis, Ioannis Papaefstathiou. 888-893 [doi]
- Interactive presentation: Implementation of a transaction level assertion framework in SystemCWolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull. 894-899 [doi]
- Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptionsShireesh Verma, Ian G. Harris, Kiran Ramineni. 900-905 [doi]
- Compositional specification of behavioral semanticsKai Chen 0003, Janos Sztipanovits, Sandeep Neema. 906-911 [doi]
- Performance analysis of multimedia applications using correlated streamsKai Huang, Lothar Thiele. 912-917 [doi]
- Simulation platform for UHF RFIDVojtech Derbek, Christian Steger, Reinhold Weiss, Daniel Wischounig, Josef Preishuber-Pfluegl, Markus Pistauer. 918-923 [doi]
- Tool-support for the analysis of hybrid systems and modelsAndreas Bauer 0002, Markus Pister, Michael Tautschnig. 924-929 [doi]
- Interactive presentation: Automatic model generation for black box real-time systemsThomas Huining Feng, Lynn Wang, Wei Zheng, Sri Kanajan, Sanjit A. Seshia. 930-935 [doi]
- Life begins at 65: unless you are mixed signal?Reimund Wittmann, Massimo Vanzi, Hans-Joachim Wassener, Navraj Nandra, Joachim Kunkel, Jose Franca, Christian Münker. 936-941 [doi]
- Routing table minimization for irregular mesh NoCsEvgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny. 942-947 [doi]
- Congestion-controlled best-effort communication for networks-on-chipJan Willem van den Brand, Calin Ciordas, Kees Goossens, Twan Basten. 948-953 [doi]
- Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chipAndreas Hansson, Martijn Coenen, Kees Goossens. 954-959 [doi]
- Testing in the year 2020Rajesh Galivanche, Rohit Kapur, Antonio Rubio. 960-965 [doi]
- Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSMGrégory Gailliard, Eric Nicollet, Michel Sarlotte, François Verdier. 966-971 [doi]
- Event driven data processing architectureIngemar Söderquist. 972-976 [doi]
- Reconfigurable system-on-chip data processing units for space imaging instrumentsBjörn Fiethe, Harald Michalik, C. Dierker, Björn Osterloh, G. Zhou. 977-982 [doi]
- Enabling certification for dynamic partial reconfiguration using a minimal flowBertrand Rousseau, Philippe Manet, D. Galerin, D. Merkenbreack, Jean-Didier Legat, F. Dedeken, Yves Gabriel. 983-988 [doi]
- Identification of process/design issues during 0.18 µm technology qualification for space applicationJulie Ferrigno, Philippe Perdu, Kevin Sanchez, Dean Lewis. 989-993 [doi]
- Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronicsPhilippe Manet, Daniel Maufroid, Leonardo Tosi, Marco Di Ciano, Olivier Mulertt, Yves Gabriel, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba. 994-999 [doi]
- WAVSTAN: waveform based variational static timing analysisSaurabh K. Tiwary, Joel R. Phillips. 1000-1005 [doi]
- Rapid and accurate latch characterization via direct Newton solution of setup/hold timesShweta Srivastava, Jaijeet S. Roychowdhury. 1006-1011 [doi]
- Temperature and voltage aware timing analysis: application to voltage dropsB. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine. 1012-1017 [doi]
- Accurate timing analysis using SAT and pattern-dependent delay modelsDesta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein. 1018-1023 [doi]
- CARAT: a toolkit for design and performance analysis of component-based embedded systemsEgor R. V. Bondarev, Michel R. V. Chaudron, Peter H. N. de With. 1024-1029 [doi]
- Modeling and simulation alternatives for the design of networked embedded systemsE. Alessio, Franco Fummi, Davide Quaglia, Maura Turolla. 1030-1035 [doi]
- Middleware design optimization of wireless protocols based on the exploitation of dynamic input patternsStylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor. 1036-1041 [doi]
- Lightweight middleware for seamless HW-SW interoperability, with application to wireless sensor networksFelix Jesús Villanueva, David Villa, Francisco Moya, Jesús Barba, Fernando Rincón, Juan Carlos López. 1042-1047 [doi]
- Interactive presentation: A middleware-centric design flow for networked embedded systemsFranco Fummi, Giovanni Perbellini, R. Pietrangeli, Davide Quaglia. 1048-1053 [doi]
- Dynamic reconfiguration in sensor networks with regenerative energy sourcesAni Nahapetian, Paolo Lombardo, Andrea Acquaviva, Luca Benini, Majid Sarrafzadeh. 1054-1059 [doi]
- Dynamic power management under uncertain informationHwisung Jung, Massoud Pedram. 1060-1065 [doi]
- Very wide register: an asymmetric register file organization for low power embedded processorsPraveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal. 1066-1071 [doi]
- Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memoryMihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram. 1072-1077 [doi]
- Interactive presentation: PowerQuest: trace driven data mining for power optimizationPietro Babighian, Gila Kamhi, Moshe Y. Vardi. 1078-1083 [doi]
- System level assessment of an optical NoC in an MPSoC platformMatthieu Briere, Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, Fabien Mieyeville, Frédéric Gaffiot, Ian O Connor. 1084-1089 [doi]
- Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architectureAbbas Sheibanyrad, Ivan Miro Panades, Alain Greiner. 1090-1095 [doi]
- Analytical router modeling for networks-on-chip performance analysisÜmit Y. Ogras, Radu Marculescu. 1096-1101 [doi]
- Interactive presentation: Hard- and software modularity of the NOVA MPSoC platformChristian Sauer, Matthias Gries, Sebastian Dirk. 1102-1107 [doi]
- The methodological and technological dimensions of technology transfer for embedded systems in aeronautics and spaceThierry Pardessus, Heinrich Daembkes, Richard Arning. 1108-1109 [doi]
- Energy evaluation of software implementations of block ciphers under memory constraintsJohann Großschädl, Stefan Tillich, Christian Rechberger, Michael Hofmann, Marcel Medwed. 1110-1115 [doi]
- An area optimized reconfigurable encryptor for AES-RijndaelMonjur Alam, Sonai Ray, Debdeep Mukhopadhyay, Santosh Ghosh, Dipanwita Roy Chowdhury, Indranil Sengupta. 1116-1121 [doi]
- Performance aware secure code partitioningSri Hari Krishna Narayanan, Mahmut T. Kandemir, Richard R. Brooks. 1122-1127 [doi]
- Energy and execution time analysis of a software-based trusted platform moduleNajwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. 1128-1133 [doi]
- Utilization of SECDED for soft error and variation-induced defect tolerance in cachesLuong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai. 1134-1139 [doi]
- Transient fault prediction based on anomalies in processor eventsSatish Narayanasamy, Ayse Kivilcim Coskun, Brad Calder. 1140-1145 [doi]
- Low-cost protection for SER upsets and silicon defectsMojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin. 1146-1151 [doi]
- Working with process variation aware cachesMadhu Mutyam, Narayanan Vijaykrishnan. 1152-1157 [doi]
- Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processorErnesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda. 1158-1163 [doi]
- Interactive presentation: Functional and timing validation of partially bypassed processor pipelinesQiang Zhu, Aviral Shrivastava, Nikil Dutt. 1164-1169 [doi]
- A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset statesIn-Ho Moon, Per Bjesse, Carl Pixley. 1170-1175 [doi]
- Estimating functional coverage in bounded model checkingDaniel Große, Ulrich Kühne, Rolf Drechsler. 1176-1181 [doi]
- Abstraction and refinement techniques in automated design debuggingSean Safarpour, Andreas G. Veneris. 1182-1187 [doi]
- Interactive presentation: Automatic hardware synthesis from specifications: a case studyRoderick Bloem, Stefan Galler, Barbara Jobstmann, Nir Piterman, Amir Pnueli, Martin Weiglhofer. 1188-1193 [doi]
- pFFT in FastMaxwell: a fast impedance extraction solver for 3D conductor structures over substrateTarek Moselhy, Xin Hu, Luca Daniel. 1194-1199 [doi]
- Optimization-based wideband basis functions for efficient interconnect extractionXin Hu, Tarek Moselhy, Jacob K. White, Luca Daniel. 1200-1205 [doi]
- Thermally robust clocking schemes for 3D integrated circuitsMosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud. 1206-1211 [doi]
- Double-via-driven standard cell library designTsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin. 1212-1217 [doi]
- Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipeliningJingye Xu, Abinash Roy, Masud H. Chowdhury. 1218-1223 [doi]
- A future of customizable processors: are we there yet?Laura Pozzi, Pierre G. Paulin. 1224-1225 [doi]
- Fast and accurate routing demand estimation for efficient routability-driven placementPeter Spindler, Frank M. Johannes. 1226-1231 [doi]
- Yield-aware placement optimizationPaolo Azzoni, Massimo Bertoletti, Nicola Dragone, Franco Fummi, Carlo Guardiani, W. Vendraminetto. 1232-1237 [doi]
- Microarchitecture floorplanning for sub-threshold leakage reductionHushrav Mogal, Kia Bazargan. 1238-1243 [doi]
- Industrial applicationsXavier Olive, Jean-Marie Pasquet, Didier Flament. 1244-1245 [doi]
- Flying embedded: the industrial scene and challenges for embedded systems in aeronautics and spaceJean Botti. 1246 [doi]
- Compact hardware design of Whirlpool hashing coreTimo Alho, Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen. 1247-1252 [doi]
- Flexible hardware reduction for elliptic curve cryptography in GF(2:::::::m:::::::)Steffen Peter, Peter Langendörfer, Krzysztof Piotrowski. 1259-1264 [doi]
- Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardwareKuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Cheng Chia Lo. 1265-1270 [doi]
- Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICsJosé Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura. 1271-1276 [doi]
- Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitryTejasvi Das, P. R. Mukund. 1277-1282 [doi]
- A two-tone test method for continuous-time adaptive equalizersDongwoo Hong, Shadi Saberi, Kwang-Ting Cheng, C. Patrick Yue. 1283-1288 [doi]
- Worst-case design and margin for embedded SRAMRobert C. Aitken, Sachin Idgunji. 1289-1294 [doi]
- Interactive presentation: Pulse propagation for the detection of small delay defectsMichele Favalli, Cecilia Metra. 1295-1300 [doi]
- Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuitsAmir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez. 1301-1306 [doi]
- A new hybrid solution to boost SAT solver performanceLei Fang, Michael S. Hsiao. 1307-1313 [doi]
- QuteSAT: a robust circuit-based SAT solver for complex circuit structureChi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang. 1313-1318 [doi]
- Boosting the role of inductive invariants in model checkingGianpiero Cabodi, Sergio Nocco, Stefano Quer. 1319-1324 [doi]
- Interactive presentation: Image computation and predicate refinement for RTL verilog using word level proofsDaniel Kroening, Natasha Sharygina. 1325-1330 [doi]
- Polynomial-time subgraph enumeration for automated instruction set extensionPaolo Bonzini, Laura Pozzi. 1331-1336 [doi]
- Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systemsMehrdad Reshadi, Daniel Gajski. 1337-1342 [doi]
- DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systemsZhiguo Ge, Weng-Fai Wong, Hock-Beng Lim. 1343-1348 [doi]
- Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformationsStefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 1349-1354 [doi]
- Interactive presentation: A process splitting transformation for Kahn process networksSjoerd Meijer, Bart Kienhuis, Alexandru Turjan, Erwin A. de Kock. 1355-1360 [doi]
- Computing synchronizer failure probabilitiesSuwen Yang, Mark R. Greenstreet. 1361-1366 [doi]
- Layout-aware gate duplication and buffer insertionDavid Bañeres, Jordi Cortadella, Michael Kishinevsky. 1367-1372 [doi]
- Self-heating-aware optimal wire sizing under Elmore delay modelMin Ni, Seda Ogrenci Memik. 1373-1378 [doi]
- Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its applicationAmith Singhee, Rob A. Rutenbar. 1379-1384 [doi]
- Clock domain crossing fault model and coverage metric for validation of SoC designYi Feng 0002, Zheng Zhou, Dong Tong, Xu Cheng. 1385-1390 [doi]
- Fast statistical circuit analysis with finite-point based transistor modelMin Chen, Wei Zhao, Frank Liu, Yu Cao. 1391-1396 [doi]
- Interactive presentation: Statistical simulation of high-frequency bipolar circuitsW. Schneider, M. Schroter, W. Kraus, H. Wittkopf. 1397-1402 [doi]
- Development and industrialisationMichel Riffiod, Paul Caspi, Christophe Piala, Jean-Luc Voirin. 1403-1405 [doi]
- Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing systemMarcus Schämann, Sebastian Hessel, Ulrich Langmann, Martin Bücker. 1406-1411 [doi]
- Mapping the physical layer of radio standards to multiprocessor architecturesCyprian Grassmann, Mathias Richter, Mirko Sauermann. 1412-1417 [doi]
- Development of an ASIP enabling flows in ethernet access using a retargetable compilation flowK. Van Renterghem, P. Demuytere, Dieter Verhulst, Jan Vandewege, Xing-Zhi Qiu. 1418-1423 [doi]
- An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chipMarco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni. 1424-1429 [doi]
- Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systemsE. Barajas, R. Cosculluela, D. Coutinho, D. Mateo, J. L. González, I. Cairò, S. Banda, M. Ikeda. 1430-1435 [doi]
- Soft error rate analysis for sequential circuitsNatasa Miskov-Zivanov, Diana Marculescu. 1436-1441 [doi]
- Verification-guided soft error resilienceSanjit A. Seshia, Wenchao Li, Subhasish Mitra. 1442-1447 [doi]
- A low-SER efficient core processor architecture for future technologiesEduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro. 1448-1453 [doi]
- Accurate and scalable reliability analysis of logic circuitsMihir R. Choudhury, Kartik Mohanram. 1454-1459 [doi]
- Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGABalkaran S. Gill, Christos A. Papachristou, Francis G. Wolff. 1460-1465 [doi]
- Design challenges at 65nm and beyondAndrew B. Kahng. 1466-1467 [doi]
- The ARTEMIS cross-domain architecture for embedded systemsHermann Kopetz. 1468-1469 [doi]
- HW/SW implementation from abstract architecture modelsAhmed Amine Jerraya. 1470-1471 [doi]
- Instruction-set customization for real-time embedded systemsHuynh Phung Huynh, Tulika Mitra. 1472-1477 [doi]
- A novel technique to use scratch-pad memory for stack managementSoyoung Park, Hae-woo Park, Soonhoi Ha. 1478-1483 [doi]
- Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparisonIsabelle Puaut, Christophe Pais. 1484-1489 [doi]
- Task scheduling for reliable cache architectures of multiprocessor systemsMakoto Sugihara, Tohru Ishihara, Kazuaki Murakami. 1490-1495 [doi]
- Fast positive-real balanced truncation of symmetric systems using cross Riccati equationsNgai Wong. 1496-1501 [doi]
- Random sampling of moment graph: a stochastic Krylov-reduction algorithmZhenhai Zhu, Joel R. Phillips. 1502-1507 [doi]
- Statistical model order reduction for interconnect circuits considering spatial correlationsJeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong. 1508-1513 [doi]
- A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technologyHengliang Zhu, Xuan Zeng, Wei Cai, Jintao Xue, Dian Zhou. 1514-1519 [doi]
- Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO sStephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain. 1520-1525 [doi]
- Accurate temperature-dependent integrated circuit leakage power estimation is easyYongpan Liu, Robert P. Dick, Li Shang, Huazhong Yang. 1526-1531 [doi]
- Low-overhead circuit synthesis for temperature adaptation using dynamic voltage schedulingSwaroop Ghosh, Swarup Bhunia, Kaushik Roy. 1532-1537 [doi]
- Maximum circuit activity estimation using pseudo-boolean satisfiabilityHratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir. 1538-1543 [doi]
- Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizingAshoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 1544-1549 [doi]
- Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scalingMyeong-Eun Hwang, Tamer Cakici, Kaushik Roy. 1550-1555 [doi]
- Towards total open source in aeronautics and space?Peggy Aycinena, Eric Bantegnie, Gerard Ladier, Ralph Mueller, Franco Gasperoni, Alex Wilson. 1556 [doi]
- A tiny and efficient wireless ad-hoc protocol for low-cost sensor networksPawel Gburzynski, Bozena Kaminska, Wladek Olesinski. 1557-1562 [doi]
- Scalable reconfigurable channel decoder architecture for future wireless handsetsGummidipudi Krishnaiah, Nur Engin, Sergei Sawitzki. 1563-1568 [doi]
- A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systemsZahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan. 1569-1574 [doi]
- Optimization of the FOCUS Inband-FEC architecture for 10-Gbps SDH/SONET optical communication channelsAfxendios Tychopoulos, Odysseas G. Koufopavlou. 1575-1580 [doi]
- A framework for system reliability analysis considering both system error tolerance and component test qualitySung-Jui (Song-Ra) Pan, Kwang-Ting Cheng. 1581-1586 [doi]
- Experimental evaluation of protections against laser-induced faults and consequences on fault modelingRégis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria. 1587-1592 [doi]
- Evaluation of design for reliability techniques in embedded flash memoriesBenoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli. 1593-1598 [doi]
- Reduction of detected acceptable faults for yield improvement via error-toleranceTong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer. 1599-1604 [doi]
- Use of statistical timing analysis on real designsA. Nardi, Emre Tuncer, S. Naidu, A. Antonau, S. Gradinaru, Tao Lin, J. Song. 1605-1610 [doi]
- A novel criticality computation method in statistical timing analysisFeng Wang 0004, Yuan Xie, Hai Ju. 1611-1616 [doi]
- Efficient computation of the worst-delay cornerLuís Guerra e Silva, Luis Miguel Silveira, Joel R. Phillips. 1617-1622 [doi]
- Accounting for cache-related preemption delay in dynamic priority schedulability analysisLei Ju, Samarjit Chakraborty, Abhik Roychoudhury. 1623-1628 [doi]
- Energy-efficient real-time task scheduling with task rejectionJian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King. 1629-1634 [doi]
- Feasibility intervals for multiprocessor fixed-priority scheduling of arbitrary deadline periodic systemsLiliana Cucu, Joël Goossens. 1635-1640 [doi]
- Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systemsMeikang Qiu, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha. 1641-1646 [doi]
- Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networksAlireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi. 1647-1652 [doi]
- Impact of process variations on multicore performance symmetryEric Humenay, David Tarjan, Kevin Skadron. 1653-1658 [doi]
- Temperature aware task scheduling in MPSoCsAyse Kivilcim Coskun, Tajana Simunic Rosing, Keith Whisnant. 1659-1664 [doi]
- Architectural leakage-aware management of partitioned scratchpad memoriesOlga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii. 1665-1670 [doi]
- Memory bank aware dynamic loop schedulingMahmut T. Kandemir, Taylan Yemliha, Seung Woo Son, Ozcan Ozturk. 1671-1676 [doi]
- System level clock tree synthesis for power optimizationSaif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal, Alexander Pratsch, Eike Schmidt. 1677-1682 [doi]